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NJU26106 -1 - dolby pro logic ii / virtual dolby surround decoder general description the NJU26106 is a digital audio signal decoder that provides the function of dolby pro logic i i and virtual dolby surround. the NJU26106 processes the stereo matrix-encoded signal into spacious sound of 5.1 channels by dolby pro logic ii and bass management system. also not matrix-encoded audio signal can be processed into effective spacious sound by music mode. the decoded 5-channel signal can be downmixed into 2-channel virtual surround output by the dolby virtual technology. the applications of the NJU26106 are suitable for multi-channel products such as av amp and car audio, or ordinary audio products such as small speaker system. features ? 5.1 channel signal outputs by dolby pro logic ii ? 2 channel outputs by virtual dolby surround ? movie mode / music mode ? available for center width control, dimension control, panorama mode music mode and custom mode ? two kinds of micro computer interface ? i 2 c bus (standard-mode/100kbps) ? 4-wire serial bus (4-wire: clock, enable, input data, output data) digital signal processor specification ? 24bit fixed-point digital signal processing ? maximum clock frequency : 40mhz ? digital audio interface : 2 input ports / 3 output ports ? power supply : dsp core : 2.5v i/o interface: 2.5v(+3.3v tolerant) i/o interface: 2.5v(+3.3v tolerant) ? package : qfp 32pin * note1: the word ?dolby?, ?pro logic? and the double d mark are trademarks of dolby laboratories. the NJU26106 can only be delivered to licensees of dolby laboratories. please refer to the licensing application manual issued by dolby laboratories. * note2: purchase of i 2 c components of new japan radio co. ,ltd or one of sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. [ [ [ [ < < < < package nju2610 6
NJU26106 - 2 - dsp block diagram fig.1-1 NJU26106 block diagram timing generator program control alu 24-bit x 24-bit multiplier address generation unit firmware rom delay ram data ram serial host interface gpio and configuration interface sdo0 sdo1 sdo2 sel1 scl/sck sda/sdout ad1/sdin ad2/ss xi xo reset dsp arithmetic unit sdi0 lri bcki mck bcko lro l/r c/lfe sl/sr serial audio interface NJU26106 sdi1 pro logic ii & virtual dolby surround decoder fig.1-2 NJU26106 function diagram prologic ii l l l l c c c c r r r r ls ls ls ls rs rs rs rs scale scale scale bass management master volume l/r balance virtual dolby surround scale l l l l c c c c r r r r ls ls ls ls rs rs rs rs sw sw sw sw noise generator lt rt left output right output center output subwoofer output leftsurround output rightsurround output prologicii and virtual dolby surround decorder block diagram scale scale delay l l l l r r r r
NJU26106 - 3 - pin configuration sdo2 sdo1 sdo0 sel1 scl/sck sda/sdout ad1/sdin ad2/ssx 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 NJU26106 vddc vddc vssc vddr vddr vssr vssr vddo xi xo vsso resetx vddc vssc test0 sdi0 vssc sdi1 test1 lri bcki mck bcko lro pin description table1-1 pin description no. symbol i/o description no. symbol i/o description 1 sdo2 o audio data output ch2 17 vddc p core power supply +2.5v 2 sdo1 o audio data output ch1 18 vddc p core power supply +2.5v 3 sdo0 o audio data output ch0 19 vssc g core gnd 4 sel1 i select i 2 c or serial bus 20 vssc g core gnd 5 scl/sck i i 2 c clock / serial clock 21 vddr p i/o power supply +2.5v 6 sda/sdout io i 2 c i/o / serial output 22 vddr p i/o power supply +2.5v 7 ad1/sdin i i 2 c address / serial input 23 vssr g i/o gnd 8 ad2/ssx i i 2 c address / serial enable 24 vssr g i/o gnd 9 vddo p osc power supply +2.5v 25 sdi_0 i audio data input ch0 10 xi i x?tal clock input 26 sdi_1 i audio data input ch1 11 xo o x?tal clock output 27 test3 i gnd 12 vsso g osc gnd 28 lri i lr clock input 13 resetx i reset 29 bcki i bit clock input 14 vddc p core power supply +2.5v 30 mck o master clock output 15 vssc g core gnd 31 bcko o bit clock output 16 test2 io open 32 lro o lr clock output ? i:in, o:out, io:bidir, p:+power, g:gnd
NJU26106 - 4 - absolute maximum ratings table1-2 absolute maximum ratings parameter symbol rating units supply voltage v dd 3.05 v pin no.10(xi) input voltage v x(osc) -0.3 3.05 v input,output pin voltage v x -0.3 3.6 v power dissipation p d 0.3 w operating temperature * t opr -20 +75 storage temperature t stg -40 +125 * for the car application, please ask njr sale. electric characteristics table1-3 electric characteristics (v dd =2.5v,ta=25 ) parameter symbol test condition min. typ. max. units operating v dd voltage v dd v dd pins 2.25 2.5 2.75 v operating current i dd f osc =36.864mhz - 60 - ma recommended operating temperature t oprr v dd =2.5v 0 25 70 high level input voltage(xi) v ih(osc) no.10pin(xi) only 2.0 - v dd v high level input voltage v ih 2.0 - 3.3 v low level input voltage v il v ss - 0.5 v high level input current i ih v in =3.3v -10 - +10 a high level input current i ih(pd) v in =3.3v 100 300 a low level input current i il v in =v ss -10 - +10 a high level output voltage v oh i oh =-2ma v dd -0.4 - - v low level output voltage v ol i ol =2ma - - 0.4 v input capacitance c in - 5 - pf input rise/fall transition time t r / t f except for no.5, 6, 7, 8pin * - - 100 ns clock frequency f osc no.10pin(xi) - - 38.0 mhz ext.system clock duty cycle r ec no.10pin(xi) 47.5 50 52.5 % * the tr / tf of these terminals is specified separately. * all input / input-and-output terminals serve as the schmidt trigger input except for no.10pin(xi).
NJU26106 - 5 - 1. clock and reset the NJU26106 xi pin requires the system clock that should be related to the sample frequency fs. the xi/xo pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator. refer to the application circuit diagram about the circuit parameters. when the external oscillator is connected to xi/xo pins, check the voltage level of the pins. because the maximum input voltage level of xi pin is deferent from the other input or bi-directional pins. the maximum voltage-level of xi pin equals to vdd. to initialize the NJU26106, reset pin should be set low level during some period. after some period of low level, reset pin should be high level. this procedure starts the initialization of the NJU26106. to finalize the initialization procedure takes 1 m sec. after 1 m sec, the NJU26106 can accept a command from host controller. the detail status of the initialized NJU26106 is referred to the each command that describes the initial status. to select i 2 c bus or 4-wire serial bus, some level should be supplied to sel1 pin. when sel1=?l?, i 2 c bus is selected. when sel1=?h?, 4-wire serial bus is selected. the level of sel1 is checked by the NJU26106 in 1 m sec after reset-pin level goes to ?h?. after the power supply and the oscillation of the NJU26106 becomes stable, reset pin should be kept low-level at least t resetx period. fig. 1-3 reset timing table 1-4 reset time symbol time t resetx R 1us osc unstable osc stable xi vdd resetx t reset x
NJU26106 - 6 - 2 system clock audio data samples must be transferred in synchronism between all components of the digital audio system. that is, for each audio sample originated by an audio source there must be one and only one audio sample processed by the NJU26106 and delivered to the d/a converters. to accomplish this, one device in the system is selected to generate the audio sample rate; the remaining devices are designated to follow this sample rate. the device that generates the audio sample rate is called the master device; all devices following this sample rate are called slave(s) lr, bck and mck should be synchronized. this is described in next section 2.1. when the NJU26106 is in master mode, the NJU26106 system clock should be 768 multiples of the sampling frequency (table2-1). when the NJU26106 is in slave mode, NJU26106 system clock should be from 768 multiples of the sampling frequency to the maximum operating frequency . 2.1 audio clock three types of clock signals are included in the serial audio interface. two of the clock signals lr (lri and lro) and bck (bcki and bcko) establish data transfer on the serial data lines. the third clock, mck, is not associated with serial data transfer but is required by delta-sigma a/d and d/a converters. the frequency of the lr clock is, by definition, equal to the digital audio sample rate, fs. bck and mck operate at multiples of the lr clock rate. therefore the signals lr, bck and mck must be locked, that is, they must be generated or derived from a single frequency reference. in slave mode, the NJU26106 dose not generate mck clock. table2- sampling frequency and bck, mck, xi clock signal multiple frequency 32khz 44.1khz 48khz lr 1fs 32khz 44.1khz 48khz bck(32fs) 32fs 1.024mhz 1.4112mhz 1.536mhz bck(64fs) 64fs 2.048mhz 2.822mhz 3.072mhz mck(256fs) 256fs 8.192mhz 11.289mhz 12.288mhz mck(384fs) 384fs 12.288mhz 16.934mhz 18.432mhz xi 768fs 24.576mhz 33.8688mhz 36.864mhz fig. 2-1 master / slave mode sdix bcko lro mc k bcki lri sdox clock divider oscillator mas ter slave xi xo
NJU26106 -7 - 3. audio interface the serial audio interface carries audio data to and from the NJU26106. industry standard serial data formats of i 2 s, msb-first left-justified or msb-first right-justified are supported. these serial audio formats define a pair of digital audio signals (stereo audio) on each data line. two clock lines, bck (bit clock) and lr (left/right word clock) establish timing for serial data transfers. the NJU26106 serial audio interface includes two data input lines; sdi0 and sdi1 and three data output lines, sdo1, sdo2, sdo3 as shown in the figure below. the input serial data is selected by the firmaware command. table 3-1 serial audio output pin description symbol pin no. description sdo0 3 front lch/rch output(*) sdo1 2 center/sub woofer output sdo2 1 rear lch/rch output (*) in virtual dolby surround mode, only front lch/rch output signal. the other channels are muted. the NJU26106 has a pair of left/right clock lines (lri and lro) and a pair of bit clock lines (bcki and bcko). clock inputs bcki and lri are used to accept timing signals from an external device when the NJU26106 is operating in slave clock mode. the bcko,lro and system clock output mck, is provided for delta-sigma a/d and d/a converters when the NJU26106 operates in master mode. in slave mode, the output of bcko and lro are the buffered output of bcki and lri. the output of mck is fixed to low level in slave mode. fig. 3-1 serial audio interface NJU26106 bcko lro mc k bcki lri serial data outputs serial clock outp uts serial clock inp uts serial data inputs sys tem cloc k for a/d, d/a c onverters (dsp master mode o nl y) sdo0 sdo1 sdo2 sdi0 sdi1
NJU26106 - 8 - 3.1 audio data format the NJU26106 can exchange data using any of three industry-standard digital audio data formats: i 2 s, msb-first left-justified, or msb-first right-justified. the three serial formats differ primarily in the placement of the audio data word relative to the lr clock. left-justified format places the most-significant data bit (msb) as the first bit after an lr transition. i 2 s format places the most-significant data bit (msb) as the second bit after an lr transition (one bit delay relative to left-justified format). right-justified format places the least-significant data bit (lsb) as the last bit before an lr transition. clock lr (lri, lro) marks data word boundaries and clock bck (bcki, bcko) clocks the transfer of serial data bits. one period of lr defines a complete stereo audio sample and thus the rate of lr equals the audio sample rate (fs). all formats transmit the stereo sample left channel first. note that polarity of lr is opposite in i 2 s format (lr:low = left channel data) compared to left-justified or right-justified formats. the number of bck clock must follow the serial data format. if the bck clock is not enough , the right sound are not produced. set serial data format for the adequate mode that a/ds ,d/as or codecs reqire. the NJU26106 supports serial data format which includes 32(32fs) or 64(64fs) bck clocks. this serial data format is applied to both master and slave mode. 3.2 serial audio data transmitting diagram fig. 3-2 left-justified data format 64fs, 24bit data fig. 3-3 right-justified data format 64fs, 24bit data fig. 3-4 i 2 s data format 64fs, 24bit data 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 left channel right channel msb m sb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 left channel right channel m sb msb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 0 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo
NJU26106 - 9 - fig. 3-5 left-justified data format 64fs, 20bit data fig. 3-6 right-justified data format 64fs, 20bit data fig. 3-7 i 2 s data format 64fs, 20bit data fig. 3-8 left-justified data format 64fs, 18bit data fig. 3-9 right-justified data format 64fs, 18bit data 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 left channel right channel msb m sb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 left channel right channel msb m sb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 0 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 left channel right channel msb msb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 0 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 left channel right channel msb m sb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo
NJU26106 - 1 0 - fig. 3-10 i 2 s data format 64fs, 18bit data fig. 3-11 left-justified data format 32fs, 16bit data fig. 3-12 right-justified data format 32fs, 16bit data fig. 3-13 i 2 s data format 32fs, 16bit data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 32 clocks 32 clocks lri, lro bcki, bcko sdi, sdo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 16 clocks 16 clocks lri, lro bcki, bcko sdi, sdo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 16 clocks 16 clocks lri, lro bcki, bcko sdi, sdo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb msb lsb lsb 16 clocks 16 clocks lri, lro bcki, bcko sdi, sdo
NJU26106 - 11 - 3.3 serial audio timing table 3-2 serial audio input timing parameters parameter symbol test condition min typ. max units bcki frequency 0.9 - 4.0 mhz bcki period l pulse width h pulse width t sil t sih 85 85 - - ns bdki to lri time t sli 40 - - ns lri to bcki time t lsi 40 - - ns data setup time t ds 40 - - ns data hold time t dh 40 - - ns fig. 3-14 serial audio input timing lri bcki sdi0,1 t ds t dh t sih t ls i t sil t sli
NJU26106 - 12 - table 3-3 serial audio output timing parameters parameter symbol test condition min typ. max units bcko period l pulse width h pulse width t sol t soh t sil -40 t sih -40 - t sil +40 t sih +40 ns bcko to lro time t slo 20 - - ns lro to bcko time t lso 20 - - ns data output delay t dod c l :lro, bcko, sdo=25pf - - 20 ns fig. 3-15 serial audio output timing lro bcko sdo0,1,2 t dod t soh t sol t slo t lso
NJU26106 - 1 3 - 4. host interface the NJU26106 can be controlled via serial host interface (shi) using either of two serial bus format : 4-wire serial bus or i 2 c bus. data transfers are in 8 bit packets (1 byte) when using either format. the shi operates only in a slave fashion. a host controller connected to the interface always drives the clock (scl / sck) line and initiates data transfers, regardless of the chosen communication protocol. the sel1 pin controls the serial bus mode. when the sel1 is low during the NJU26106 initialization, 4-wire serial bus is available. when the sel1 is high during the NJU26106 initialization, i 2 c bus is available. table 4-1 serial host interface pin description symbol (i 2 c / serial) pin no. 4-wire serial bus format i 2 c bus format scl/sck 5 serial clock serial clock sda/sdout 6 serial data output serial data (bi-directional) ad1/sdin 7 serial data input i 2 c bus address bit1 ad2/ssx 8 slave select i 2 c bus address bit2 note : sda /sdout pin is a bi-directional open drain. when 4-wire serial bus is selected, and ssx is effective, and a cmos output and ssx are invalid, it will be in a hi-z state. this pin, which is assigned for 4-wire serial bus format or for i 2 c, requires a 4.7k pull-up resister. 4.1 4-wire serial interface the serial host interface can be configured for 4-wire serial bus communication by setting sel1=?h? during the reset sequence initialization. shi bus communication is full-duplex; a write byte is shifted into the sdin pin at the same time that a read byte is shifted out of the sdout pin. data transfers are msb first and are enabled by setting the slave select pin low (ssx = 0). data is clocked into sdin on rising transitions of sck. data is latched at sdout on falling transitions of sck except for the first byte (msb) which is latched on the falling transitions of ssx. sdout is hi-z in case of ssx = ?h?. sdout is cmos output in case of ssx = ?l?. sdout needs a pull-up resistor when sdout is hi-z.
NJU26106 - 14 - table 4-2 4-wire serial interface timing parameters parameter symbol timelines min. typ. max. units input data rising time t msdr a-b - - 100 ns input data falling time t msdf a-b - - 100 ns serial clock rising time t mscr d-e - - 100 ns serial clock falling time t mscf f-g - - 100 ns serial strobe rising time t mssr p-q - - 100 ns serial strobe falling time t mssf m-n - - 100 ns serial clock h duration t msca e-f 50 - - ns serial clock l duration t mscn g-h 50 - - ns serial clock period t mscc e-i 250 - ns serial strobe setup time t msss n-e 100 - ns serial strobe hold time t mssh j-q 30 - ns serial strobe l duration t mssa n-p - 1.0 - s serial strobe h duration t mssn q-r 40 - ns input data setup time t msdis b-e 20 - ns input data hold time t msdih e-c 20 - ns output data delay (from ssx) t msdos n-o,cl=25pf - - 50 ns output data delay (from sclk) t msdo g-k(data-6), cl=25pf - - 50 ns output data hold time t msdoh g-k(data-7) 0 - - ns output data turn off time (hi-z) t msdov q-l - - 40 ns fig. 4-1 4-wire serial interface timing note : *1 when the data-clock is less than 8 clocks, the input data is shifted to lsb side and is sent to the dsp core at the transition of ssx=?h?. *2 when the data-clock is more than 8 clocks, the last 8 bit data becomes valid. *3 after sending lsb data, sdout transmits the msb data which is received via sdin until ssx becomes ?h?. *4 sdout is hi-z in case of ssx = ?h?. sdout is cmos output in case of ssx = ?l?. sdout needs a pull-up resistor to prevent sdout from becoming floating level . m n o ssx p q r a c b 7 6 5 1 0 sdin l k 7 6 5 1 0 sdout d f g h j i sck e hi-z hi-z msb lsb note (3)
NJU26106 - 1 5 - 4.2 i 2 c bus when the NJU26106 is configured for i 2 c bus communication in sel1=?l?, the serial host interface transfers data on the sda pin and clocks data on the scl pin. sda is an open drain pin requiring an external 4.7k pull-up resistor. pins ad1 and ad2 are used to configure the seven-bit slave address of the serial host interface. this offers additional flexibility in a system design by offering two different possible slave addresses for which the NJU26106 will respond to. an address can be arbitrarily set up with an internal setup and this ad1 terminal. in the NJU26106, ad2 pin should be connected to ?h?. any i 2 c address could be chosen for ad1. the i 2 c address of ad1 is decided by connection of ad1-pin. the i 2 c address should be the same level of ad1-pin . table 4-3 i 2 c bus slave address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 1 1 1 ad2* 1 ad1* 2 r/w *1 ad2 pin should be connected to high. the ii 2 c address of ad2 should be 1. *2 slave address is 0 when ad1 is l. slave address is 1 when ad1 is h. the figure on the following page shows the basic timing relationships for transfers. a transfer is initiated with a start condition, followed by the slave address byte. the slave address consists of the seven-bit slave address followed by a read/write (r/w) bit. when an address with an effective serial host interface is detected, the acknowledgement bit which sets a sda line to low in the ninth bit clock cycle is returned. the r/w bit in the slave address byte sets the direction of data transmission until a stop condition terminates the transfer. r/w = 0 indicates the host will send to the NJU26106 while r/w = 1 indicates the host will receive data from the NJU26106. fig. 4-2 i 2 c bus format in case of the NJU26106, only single-byte transmission is available. the serial host interface supports ?standard-mode (100kbps)? i 2 c bus data transfer. 1-7 8 9 1-7 8 9 s p sda scl address data ack ack r/w start stop
NJU26106 - 1 6 - table 4-4 i 2 c bus interface timing parameters standard mode parameter symbol min max units scl clock frequency f scl 0 100 khz start condition hold time t hd:sta 4.0 - s scl ?l? duration t low 4.7 - s scl ?h? duration t high 4.0 - s start condition setup time t su:sta 4.7 - s data hole time t hd:dat 0 3.45 s data setup time t su:dat 250 - ns rising time t r - 1000 ns falling time t f - 300 ns stop condition setup time t su:sto 4.0 - s bus release time t buf 4.7 - s fig. 4-3 i 2 c bus timing sda t bu f t hd:st a sr p t low t r t hd:dat t high t f t su:dat s p t su:st a t su:st o t hd:st a scl
NJU26106 - 17 - 5. firmware command table the NJU26106 allows for user configuration of the decoder with micro controller commands entered via host interface (i 2 c bus or serial interface). the following table summarizes the available user commands . table5-1 NJU26106 command no. command system command description 1 set_task_cmd set decoding mode: pro logic ii, virtual dolby surround, pink noise generator 2 vds_ang_cmd set virtual dolby surround speaker separation angle 3 dpl_sur_cmd set pro logic ii decode mode (movie,music,etc) and panorama mode 4 cwidth_dim_cmd set pro logic ii center width and dimension configuration 5 dpl_mod_cmd set pro logic ii variable setting, auto input balance and shelf filter, rs polarity inversion, etc 6 bass_mgnt_cmd set bass management configuration, lfe cutoff frequency configuration 7 fs_cmd set sampling rate 8 noise_cmd set output speaker configuration for pink noise generator 9 dly_cmd set surround channel delay time 10 lr_bal_cmd set l/r volume balance 11 mst_vol_cmd set master volume 12 lch_vol_cmd set l channel volume 13 rch_vol_cmd set r channel volume 14 cent_vol_cmd set center channel volume 15 surr_left_vol_cmd set surround left channel volume 16 surr_right_vol_cmd set surround right channel volume 17 sw_vol_cmd set subwoofer channel volume 18 sys_set_cmd configure serial audio interface format, lr & bck master/slave, etc.
NJU26106 - 1 8 - package dimensions (eiaj : qfp032-p-0707-1) ver. 2.1 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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